How much current does a transistor deliver?
180 nm is the shortest gate this process can print, 0.22 µm the narrowest device. Both length and width are adjustable below. This exercise starts at the minimum length and establishes how drive current scales with width.
- Press Run the sweeps.
- On the first plot, follow one curve left to right: it climbs, then flattens. The dashed line joins every curve's knee and marks the border — triode to its left, saturation to its right.
- Read the flat current — that is IDsat. Now look at the table: when W doubles, does it double too?
- Set Device to Compare. How much weaker is the PMOS at the same width?
Output characteristic
one curve per VGSFindingOutput resistance appears here once the sweeps have run with Device set to NMOS or PMOS.
The same sweep at VGS = VDD
one curve per widthFindingRun the sweeps to fill this in.
Transfer characteristic
threshold voltageFindingThe threshold appears here once the sweeps have run.
Turning current into time
A transistor is a switch with resistance, and every node in a chip has capacitance. Timing how long one takes to move the charge on the other is the point where drive current turns into switching speed.
- Press Run the transient. The NMOS starts holding a charged capacitor and pulls it down to ground.
- Read the 90 % → 10 % time in the table, once per width.
- Check the last column, W × t. If it barely moves, then t goes as 1/W. The narrowest device drifts about ten percent below the rest — the edge effect from 1A, reappearing here as a difference in discharge time.
- Then double the capacitance and run again: how does the time change?
- Set Device to PMOS charge: the same capacitor is now filled from VDD through a PMOS. Then set Compare — at equal width, how much longer does filling take than emptying?
Output node during the discharge
transientDischarge time
90 % → 10 %FindingPress Run the transient to fill this in.
Why this inverter is wrong, and how to fix it
An inverter built with an equally wide NMOS and PMOS: the obvious choice, and the wrong one. Run it, look at the two output edges, then fix it.
- Press Run the transient. In the plot, the output drops quickly but climbs slowly — read tpHL and tpLH in the table to quantify the difference.
- Both devices are the same width — so what differs between them?
- Press Find the balance point. The two curves cross where the edges match — that crossing is the required ratio.
- Note that the crossing is a ratio, while the field takes a multiple of W0. The Finding underneath has already multiplied it by Wn — enter that number as Wp and run again: the two edges become symmetric and VM climbs toward VDD/2.
Transient response
input and outputFindingRun the transient to fill this in.
Propagation delay against the width ratio
sizing sweepFindingPress Find the balance point to see where the two delays cross.
DC transfer characteristic
switching thresholdFindingVM appears here once the transient has run.
Keeping the delay when the load grows
Gates drive other gates. The first measurement establishes the load one gate presents to its driver; the second poses the question this session has been leading to: if the load grows eight times, what stops the circuit getting eight times slower?
- Press Measure one gate's input capacitance. It drives three real gates, then finds the single capacitor that behaves the same.
- Press Scale the load…. Blue scales the driver together with the load; orange keeps the driver at its original size.
- Read the table. One tpHL column barely moves while the other climbs with the load — which one, and why?
- The constant delay was not free. What did it cost?
Delay as the load grows
scaled vs fixed driverFindingPress Scale the load, with and without the driver to fill this in.
Three real gates against one capacitor
equivalent loadFindingPress Measure one gate's input capacitance to fill this in.